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| EM78M611 Universal Serial Bus Microcontroller Series Preliminary 1. General Description SPECIFICATION The EM78M611 is a series of Universal Serial Bus 8-bit RISC Multi-Time Programming (MTP) microcontrollers. It is specifically designed for USB low speed device application and to support legacy device such as PS/2 keyboard. The EM78M611 also support one device address and three endpoints. With no firmware involved, these series of microcontrollers can automatically identify and decode Standard USB Command to EndPoint Zero. The EM78M611 is implemented on a RISC architecture. It has eight-level stack and eight interrupt sources. Each device has 144 bytes of general purpose SRAM and 6K bytes of program ROM, and is embedded with 4 bytes of E2PROM. The EM78M611 has up to 11 pins with the capacity of sinking large current. These series of chips have many powerful features, including : Dual Clock mode which allows the device to run on very low power saving frequency Pattern Detect Application function which is used in a serial transmission to count waveform width Width Modulation that can generate a duty-cycle-programmable signal 24-channel AD converter with up to 10 bits resolution. 2. Features Operating voltage 4.4V ~ 5.25V Low-cost solution for low-speed USB devices, such as keyboard, joystick, and Gamepad. USB Specification Compliance Universal Serial Bus Specification Version 1.1 USB Device Class Definition for Human Interface Device (HID), Firmware Specification Version 1.1 Support 1 device address and 3 endpoints USB Application P75(D-) has an internal pull-high resistor (1.5K Ohm) USB protocol handling USB device state handling Identifying and decoding of Standard USB commands to EndPoint Zero This spec. may change without further notice. 1 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary PS/2 Application Support Auto-detects PS/2 or USB port Build-in PS/2 port interface for keyboard and mouse Built-in 8-bit RISC MCU 8 level stacks for subroutine and interruption Eight available interruptions 8-bit real time clock/counter (TCC) with overflow interruption Built-in RC oscillator free running for WatchDog Timer and Dual clock mode Two independent programmable prescalers for WDT and TCC Two methods of saving power: 1. Power-down mode (SLEEP mode) 2. Dual clock mode. Two clocks per instruction cycle Multi-time programmable I/O Ports Up to 11 LED sink pins Each GPIO pin of Ports 5, 6, 8, P90~P93, P95, and P96; has an internal programmable pull-high resistor (25K Ohm) Each GPIO pin of Port 6, P74~P77, and Port 9 can wakeup the MCU from sleep mode by input state change Internal Memory Built-in 6K*13 bits Program ROM Built-in 144 bytes general purpose registers (SRAM) Built-in USB Application FIFOs. Built-in 4 bytes E2PROM Operation Frequency Normal Mode: MCU runs at the external oscillator frequency; 6MHz or 12MHz Dual Clock Mode: MCU runs at the frequency of 256KHz (or 32KHz, 4KHz, 500Hz), emitted by the internal oscillator with the external ceramic resonator (or crystal) turned off to save power. Built-in Pattern Detect Application for serial signal transmission Built-in Pulse Width Modulation (PWM) Up to 2 channels PWM function on P.92 (PWM1) and P.93 (PWM2). This spec. may change without further notice. 2 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary Up to 8-bit resolution PWM output Up to 8 selections of duty cycles Built-in 24-Channel Analog-to-Digital Converter (ADC) Up to 24 channels Up to 10 bits resolution 4 ADC conversion rates: 256K/12K/64K/32K Built-in 3.3V Voltage Regulator For MCU power supply Pull-up source for the external USB resistor on D-pin. Package Type: 40 pin PDIP (EM78M611(A/B/C/D) AP) 44 pin QFP (EM78M611(A/B/C/D) AQ) 20 pin PDIP/SOP (EM78M611(A/B/C/D) BP/BM) 20 pin SSOP (EM78M611(A/B/C/D) DM) 24 pin PDIP/SOP (EM78M611(A/B/C/D) CP/CM) 3. Type Definition The EM78M611 series has 4 types of packaging. Each type is divided into 4 modules, namely; original, with E2PROM, with A/D converter, and with both E2PROM and A/D converter. The Table 3.1 below summarizes which series of the EM78611 belong to which module. Original EM78M611A With E PROM EM78M611B 2 With A/D Converter EM78M611C With Both EM78M611D Table 3-1 Packaging Summary of EM78M611 Series IC This spec. may change without further notice. 3 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 4. Applications USB Keyboard only. USB and PS/2 both compatible with Keyboard. USB Keyboard with USB Mouse. USB Joystick. This spec. may change without further notice. 4 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 5. Pin Configuration EM78M611AP (40-Pin DIP) VSS V3.3 D+ / CLK / P74 D- / DATA / P75 P90 P91 P92 / PWM1 / SE1 P93 / PWM2 / SE2 P94/Vpp VNN P50 / AD0 P51 / AD1 P52 / AD2 P53 / AD3 P54 / AD4 P55 / AD5 P56 / AD6 P57 / AD7 P80 / AD8 P81 / AD9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OSCO OSCI VDD P70 P71 P72 P67 / AD23 P66 / AD22 P65 / AD21 P64 / AD20 P63 / AD19 P62 / AD18 P61 / AD17 P60 / AD16 P87 / AD15 P86 / AD14 P85 / AD13 P84 / AD12 P83 / AD11 P82 / AD10 EM78M611AQ (44-Pin QFP) D- / DATA / P75 D+ / CLK / P74 OSCO OSCI VDD V3.3 VSS P90 P76 P77 35 44 43 42 41 40 39 38 37 36 P91 P92 / PWM1 / SE1 P93 / PWM2 / SE2 P94/Vpp P95 P96 VNN P50 / AD0 P51 / AD1 1 2 3 4 5 6 7 8 9 34 33 32 31 30 29 28 27 26 25 24 23 * P70 P71 P72 P67 / AD23 P66 / AD22 P65 / AD21 P64 / AD20 P63 / AD19 P62 / AD18 P61 / AD17 P60 / AD16 P87 / AD15 P52 / AD2 10 P53 / AD3 11 12 13 14 15 16 17 18 19 20 21 P85 / AD13 22 P86 / AD14 P82 / AD10 P83 / AD11 P54 / AD4 P55 / AD5 P56 / AD6 P57 / AD7 P80 / AD8 P81 / AD9 This spec. may change without further notice. 5 P84 / AD12 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary EM78M611BP/BM/DM (20-Pin PDIP/SOP/SSOP) P56/AD6 P57/AD7 P60/AD16 P61/AD17 P62/AD18 P77 P76 VDD OSCI OSCO 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P55 / AD5 P54 / AD4 VNN P94/Vpp P93 / PWM2 / SE2 P92 / PWM1 /SE1 D- / DATA / P75 D+ / CLK / P74 V3.3 VSS EM78M611CP/CM (24-Pin PDIP/SOP) OSCO VSS V3.3 D+ / CLK / P74 D- / DATA / P75 P92 / PWM1 /SE1 P93 / PWM2 / SE2 P94/Vpp VNN P54 / AD4 P55 / AD5 P56 / AD6 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OSCI VDD P76 P77 P66 / AD22 P65 / AD21 P64 / AD20 P63 / AD19 P62 / AD18 P61 / AD17 P60 / AD16 P57 / AD7 This spec. may change without further notice. 6 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 6. Pin Description Pin Number P50 ~ P57 P60 ~ P67 P80 ~ P87 AD0 ~ AD23 P90 ~ P93 P95 ~ P96 PWM1 ~ PWM2 SE1 ~ SE2 P70 ~ P72, P76, P77 I/O I/O I I/O O I I/O Function GPIO pins. These pins can be pulled-high internally through software control. Analog to Digital Converter input pins. GPIO pins. These pins can be pulled-high internally through software control or LED sink pins. PWM output pins Serial Signal input pins. LED sink pins. P76, P77 will have an internal pulled-high resistor when the EM78M611 is running under PS/2 mode. USB plus data line interface or CLK for PS/2 keyboard. When the EM78M611 is running under PS/2 mode, this pin will have an internal pulled-high resistor (2.2K Ohm), with VDD=5.0V. USB minus data line interface or DATA for PS/2 keyboard. When the EM78M611 is running under PS/2 mode, this pin will have an internal pulled-high resistor (2.2K Ohm), with VDD=5.0V. When the EM78M611 is running under USB mode, this pin will have an internal pulled-high resistor, 1.5k Ohm, with V3.3=3.3V. 6MHz / 12MHz ceramic resonator or crystal input. Return path for 6-MHz / 12MHz ceramic resonator or crystal. Power supply pin. Ground pin. MTP program Pin Input only I/O. MTP program pin. 3.3v regulator output. D+ / CLK / P74 I/O D- / DATA / P75 I/O OSCI OSCO VDD GND VNN P94/VPP V3.3 I O PWR PWR I I PWR This spec. may change without further notice. 7 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 7. Block Diagram OSCI OSCO VDD V3.3 D+ DR2 (PC) Stack1 Stack2 Stack3 Built-in RC Oscillator Tim ing Control 3.3V Regulator Transceiver Stack4 ROM Stack5 Stack6 USB Device Controller Stack7 Stack8 Instruction register R3 (Status) EEPROM Prescaler W DT Reset & Sleep & W ake up Control Prescaler TCC RAM Interrupt Control ALU Instruction Decoder ACC W DT Tim er R1 (TCC) R4 (RSR) DATA & CO NTROL BUS PW M ADC P90 P91 P92/PW M1/SE1 P93/PW M2/SE2 P94/Vpp P95 P96 P80/AD P81/AD P82/AD P83/AD P84/AD P85/AD P86/AD P87/AD P60/AD P61/AD P62/AD P63/AD P64/AD P65/AD P66/AD P67/AD P50/AD P51/AD P52/AD P53/AD P54/AD P55/AD P56/AD P57/AD P74/D+/Clk P75/D-/Data I/O Port 7 P70 P71 P72 P76 P77 Pattern Detect Application I/O Port 9 I/O Port 8 I/O Port 6 I/O Port 5 8. Function Description The EM78M611memory is organized into four spaces, namely; User Program memory in 2 6K*13 bits ROM space, Data Memory in 144 bytes SRAM space, E PROM space, and USB Application FIFOs for EndPoint0, EndPoint1, and EndPoint2. Furthermore, several registers are used for special purposes. 8.1 Program Memory The program space of the EM78M611 is 6K bytes, and is divided into six pages. Each page is 1K bytes long. After Reset, the 13-bit Program Counter (PC) points to location zero of the program space. The Interrupt Vector is at 0x0001 and accommodates TCC interrupt, RF1(SE1) timing counter interrupt, RF2(SE2) timing counter interrupt, P74~P77 State Changed interrupt, EndPoint 0 interrupt, USB Suspend interrupt, USB Reset interrupt, and USB Host Resume interrupt. After an interrupt, the MCU will fetch the next instruction from the corresponding address as This spec. may change without further notice. 8 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary illustrated in the following diagram. This spec. may change without further notice. 9 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary After reset PC 0x0000 0x0001 0x03FF 0x0400 0x07FF 0x0800 0x0BFF 0x0C00 0x0FFF 0x1000 0x13FF 0x1400 0x17FF Address Reset Vector Interrupt Vector Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 8.2 Data Memory The Data Memory has 144 bytes SRAM space. It is also equipped with USB Application FIFO space for USB Application. The Figure 8.1 (next page) shows the organization of the Data Memory Space. 8.2.1 Special Purpose Register When the microcontroller executes instruction, specific registers are invoked for assistance, such as; Status Register which records the calculation status, Port I/O Control Registers which control the I/O pins' direction, etc. EM78M611 provides a lot of other special purpose registers for different functions. Note that Special Control Registers can only be read or written by two instructions: IOR and IOW. This spec. may change without further notice. 10 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 : 1F R0 R1(TCC) R2(PC) R3(Statu s) R4(RSR ) R5(Port 5) R6(Port 6) P7(Port 7) R8(Port 8) R9(Port 9) RA(EEC R) RB(PD ACR) RC(U SBSR) RD(FIFOA) RE(FIFODR) RF(ISR) Stack (8 le s) vel 0 1 2 3 4 5 6 7 00 Endpoi 0 nt 01 EndPoin t : address 0F 0_statu s 10 EP 11 : 1F EP _statu s IOC5 IOC6 IOC7 IOC8 IOC9 IOCA IOCB IOCC IOCD IOCE IOCF ERA(ADCR/AD_Se l) ERB(AD _LSB ) ERC(AD _MSB) ERD(AD Rate) ERE( WM_CNT) P 16x8 Com m on Register 00 20 21 : 3F 01 10 11 32x8 Bank Regi ter (Bank0) s 32x8 B ank Regi ter (B s ank1) 32x8 Ba k n Regi ter (Ba s nk2) 32x8 Bank Regi ter (Bank3 s ) Fig 8.1 The Organization of EM78M611 Data RAM 8.2.1.1 Operation Registers The following sections will introduce each of the Operation Registers of the Special Purpose Registers. The Operation Registers are arranged according to the order of registers' address. Note that some registers are read only, while others are both readable and writable. R0 (Indirect Addressing Register) Default Value: (0B_0000_0000) R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses the data pointed by the RAM Select Register (R4). This spec. may change without further notice. 11 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary R1 (Time / Clock Counter) Default Value: (0B_0000_0000) This register TCC, is an 8-bit timer or counter. It is readable and writable as any other register. After Power-on reset and WatchDog reset, the initial value of this register is 0x00. R2 (Program Counter & Stack) Default Value: (0B_0000_0000) The EM78M611 Program Counter is a 13-bit long register that allows accessing 6k bytes of Program Memory with 8 level stacks. The eight LSB bits, A0~A7, are located at R2, while the three MSB bits, A12~A10, are located at R3. The Program Counter is cleared after Power-on reset or WatchDog reset. The first instruction that is executed after a reset is located at address 00h. CALL A12 A11 A10 A9 0000 000 Page 0 03FF 0400 001 Page 1 07FF 0800 010 Page 2 0BFF 0C00 011 Page 3 0FFF 100 1000 Page 4 13FF 101 1400 Page 5 17FF A8 A7 ~ A0 RET RETL RETI Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 Stack 7 Stack 8 000 : Reset location This spec. may change without further notice. 12 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary R3 (Status Register) Default Value:(0B_0001_1XXX) 7 PS2 6 PS1 5 PS0 4 T 3 P 2 Z 1 DC 0 C R3 [0] R3 [1] R3 [2] Carry flag. Auxiliary carry flag. Zero flag. It will be set to 1 when the result of an arithmetic or logic operation is zero. Power down flag. It will be set to 1 during Power-on phase or by "WDTC" command and cleared when the MCU enters into Power down mode. It remains in previous state after WatchDog Reset. 1: Power-on. 0: Power down R3 [3] R3 [4] Time-out flag. It will be set to 1 during Power-on phase or by "WDTC" command. It is reset to 0 by WDT time-out. 1: WatchDog timer no overflow. 0: WatchDog timer overflow. The various states of Power down flag and Time-out flag at different conditions are shown below: T 1 1 0 1 1 P 1 1 *P 0 0 Condition Power-on reset WDTC instruction WDT time-out Power down mode Wakeup caused by port change during Power down mode *P: Previous status before WDT reset R3 [5-7] Page selection bits. These three bits are the used to select the page of program memory. PS2 0 0 0 0 1 1 PS1 0 0 1 1 0 0 PS0 0 1 0 1 0 1 Program Memory Page [Address] Page 0 [0000-03FF] Page 1 [0400-07FF] Page 2 [0800-0BFF] Page 3 [0C00-0FFF] Page 4 [1000-13FF] Page 5 [1400-17FF] This spec. may change without further notice. 13 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary R4 (RAM Select Register) Default Value: (0B_00XX_XXXX) 7 BK1 6 BK0 5 Ad5 4 Ad4 3 Ad3 2 Ad2 1 Ad1 0 Ad0 R4 (RAM select register) contains the address of the registers. R4 [0~5] are used to select registers in 0x00h~0x3Fh. The address 0x00~0x1F is common space. After 0x1Fh, SRAM are divided into four banks. Use Bank Select Register. R4 [6,7] to select the registers bank (refer to the table below).The following are two examples: (1) R4=0001100 and R4=1001100 point to the same register 0x0Ch. Since 0x0Ch is in the common space, Bit 6 and Bit 7 are meaningless. (2) R4=0111100 points to the register 0x3C in Bank 2. R4[7]Bk1 0 0 1 1 R4[6]Bk0 0 1 0 1 RAM Bank # Bank 0 Bank 1 Bank 2 Bank 3 R5 (Port5 I/O register) Default Value: (0B_0000_0000) 7 P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 R6 (Port 6 I/O register) Default Value: (0B_0000_0000) 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 R7 (Port7 I/O register) Default Value: (0B_0000_0000) 7 P77 6 P76 5 D- / P75 / DATA 4 D+ / P74 / CLK 3 2 P72 1 P71 0 P70 R8 (Port 8 I/O register) Default Value: (0B_0000_0000) 7 P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 R9 (Port 9 I/O register) 7 6 P96 5 Default Value: (0B_0000_0000) 4 P94 3 P93 2 P92 1 P91 0 P90 P95 This spec. may change without further notice. 14 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary This spec. may change without further notice. 15 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary RA (E2PROM Control Register) Default Value: (0B_0000_0011) RA is a command register for E2RPOM control. For detailed usage of this register, refer to Section 8.2.3 which describes the E2RPOM embedded in the EM78M611. RB (Pattern Detect Application Control Register) Default Value: (0B_0000_0000) RB is a control register for controlling the Pattern Detect Application function. For the detailed description of this register, refer to Section 8.7.2 which describes the PDA function. RC (USB Application Status Register) Default Value: (0B_0000_0000) 7 EP0_W 6 EP0_R 5 EP1_R 4 EP2_R 3 EP2_W 2 1 0 Stall Host_Suspend EP0_Busy RC [0] Stall flag While MCU receives an unsupported command or invalid parameters from host, this bit will be set to 1 by the firmware to notify the UDC to return a STALL handshake. When a successful SETUP transaction is received, this bit is cleared automatically. This bit is readable and writable. RC [1] EP0_Busy flag When this bit is equal to "1," it indicates that the UDC is writing data into the EP0'FIFO or reading data from it. During this time, the firmware will avoid accessing the FIFO until UDC finishes writing or reading. This bit is only readable. RC [2] Host Suspend flag If this bit is equal to 1, it indicates that USB bus has no traffic for the specified period of 3.0 ms. This bit will also be cleared automatically when there is bus activity. This bit is only readable. RC [3] EP2_W flag This bit is set when the UDC receives a successful data from USB Host to EP2. Upon detecting that this bit is equal to One, the firmware will execute a read sequence to the EP2's FIFO, then clear this bit. Otherwise, the subsequent data from USB Host won't be accepted by the UDC. RC [4,5,6] EP0_R / EP1_R / EP2_R flag These three bits inform the UDC to read the data written by the firmware from the FIFO. Then the UDC will send the data to the Host automatically. After UDC finishes reading the data from the FIFO, this bit will be cleared automatically. Therefore, before writing data into FIFO's, the firmware will first check this bit to avoid overwriting the data. These two bits can only be set by the firmware and cleared by the hardware. This spec. may change without further notice. 16 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary RC [7] EP0_W flag After the UDC completes writing data to the FIFO, this bit will be set automatically. The firmware will clear it as soon as it gets the data from EP0's FIFO. Only when this bit is cleared that the UDC will be able to write a new data into the FIFO. Therefore, before the firmware can write a data into the FIFO, this bit must first be set by the firmware to prevent UDC from writing data at the same time. This bit is both readable and writable. RD (USB Application FIFO Address Register) Default Value: (0B_0000_0000) 7 0 6 0 5 0 4 UAD4 3 UAD3 2 UAD2 1 UAD1 0 UAD0 RD [0~4] USB Application FIFO address registers. These five bits are the address pointer of USB Application FIFO. Undefined registers. The default value is zero. RD [5~7] RE (USB Application FIFO Data Register) Default Value: (0B_0000_0000) 7 UD7 6 UD6 5 UD5 4 UD4 3 UD3 2 UD2 1 UD1 0 UD0 RE (USB Application FIFO data register) contains the data in the register of which address is pointed by RD. RF (Interrupt Status Register ) Default Value: (0B_0000_0000) 7 6 5 SE1_IF 4 3 2 1 0 TCC_IF USB Host SE2_IF Resume_IF Port7 state USB USB EP0_IF change_1F Reset_IF Suspend_IF RF [0] TCC Overflow interrupt flag. It will be set while TCC overflows, and is cleared by the firmware. EndPoint Zero interrupt flag. It will be set when the EM78M611 receives Vender /Customer Command to EndPoint Zero. This bit is cleared by the firmware. USB Suspend interrupt flag. It will be set when the EM78M611 finds the USB Suspend Signal on USB bus. This bit is cleared by the firmware. USB Reset interrupt flag. It will be set when the host issues the USB Reset signal. Port 7 State Change interrupt flag. It will be set at P.74 ~ P.77 State Change when the EM78M611 is not running under USB mode. RF [1] RF [2] RF [3] RF [4] This spec. may change without further notice. 17 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary RF [5,6] SE1 / SE2 Pattern Detection interrupt flag. These two flags are used for Pattern detecting application. USB Host Resume interrupt flag. It will be set only under Dual clock mode when the USB suspend signal becomes low. RF [7] 8.2.1.2 Control Registers Some special purpose registers are available for special control purposes. Except for the Accumulator (A), these registers must be read and written by special instructions. One of these registers, CONT, can only be read by the instruction "CONTR" and written by "CONTW" instruction. The other special control registers can be read by the instruction "IOR" and written by the instruction "IOW." The following paragraphs only describe the general functions of the control registers. For more detailed description, refer to Sections 8.7 to 8.9 of this spec. A (Accumulator Register) The accumulator is an 8-bit register that holds operands and results of arithmetic calculations. It is not addressable. CONT (Control Register) Default Value: (0B_0011_1111) 7 LED 6 /INT 5 TSR2 4 TSR1 3 TSR0 2 PSR2 1 PSR1 0 PSR0 Except for Bit-6 (Interrupt enable control bit), CONT register can be read by the instruction "CONTR" and written by the instruction "CONTW." CONT [0~2] WatchDog Timer prescaler bits. These three bits are used as the prescaler of WatchDog Timer. CONT [3~5] TCC Timer prescaler bits. The relationship between the prescaler value and these bits are shown below: PSR2/TSR2 0 0 0 0 1 1 1 1 PSR1/TSR1 0 0 1 1 0 0 1 1 PSR0/TSR0 0 1 0 1 0 1 0 1 TCC Rate 1: 2 1: 4 1: 8 1: 16 1: 32 1: 64 1: 128 1: 256 WDT Rate 1: 1 1: 2 1: 4 1: 8 1: 16 1: 32 1: 64 1: 128 This spec. may change without further notice. 18 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary CONT [6] Interrupt enable control bit. This bit toggles Interrupt function between enable and disable. It is set to 1 by the interrupt disable instruction "DISI" and reset by the interrupt enable instructions "ENI" or "RETI." 0: Enable the Interrupt function. 1: Disable the Interrupt function. Note that this bit can be read only by the instruction "CONTR" CONT [7] LED bit. This bit is used to enable the LED sink capacity of P76 and P77. 0: Disable the LED sink capacity of P76, P77. 1: Enable the LED sink capacity of P76, P77. IOC5 ~IOC9 I/O Port Direction Control Registers These are I/O port (Port5 ~ Port7) direction control registers. Each bit controls the I/O direction of three I/O ports respectively. When these bits are set to 1, the relative I/O pins become input pins. Similarly, the I/O pins becomes outputs when the relative control bits are cleared. 1: Input direction. 0: Output direction. IOCA (Operation Mode Control Register) Default Value: (0B_1100_0000) 7 Dual_Frq.1 6 Dual_Frq.0 5 4 3 ExReg_Sel 2 PDA 1 PS/2 0 USB IOCA [0,1] These two bits are used to select the operation mode. EM78M611 can auto-detect the type of port device being attached. After identifying the port, the firmware will set these two bits to enter into a proper operation mode. The definition of these two control registers is described in the table below. IOCA[1] 0 0 1 1 IOCA[0] 0 1 0 1 Operation Mode Detect Mode USB Mode PS/2 Mode USB Test Mode IOCA [2] Pattern Detect Application function enable bit. This bit is used to enable the Pattern Detect Application (PDA) function. For the details about this function please refer Section 8.7. 0: Disable PDA function. 1: Enable PDA function. This spec. may change without further notice. 19 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary IOCA [3] Extra control register select bit. The five extra control registers (ERA, ERB, ERC, ERD, and ERD) are located in 0xA~0xE. To access these five registers, set the bit as follows: 0: Select RA ~ RE. 1: Select Extra Control registers - ERA ~ ERE. IOCA [6,7] Selects the operation frequency in Dual Clock Mode. Four frequencies are available and can be chosen as Dual Clock Mode for running the MCU program. Dual_Frq.1 0 0 1 1 Dual_Frq.0 0 1 0 1 Frequency 500Hz 4kHz 32kHz 256kHz IOCB (Port 9 Wake-up Pin Select Register) Default Value: (0B_1111_1111) 7 1 6 /P96 5 /P95 4 /P94 3 /P93 2 /P92 1 /P91 0 /P90 IOCB [0~6] These bits are used to select which of the Port 9 pins is to be assigned to wakeup the MCU while in Power down mode. 0: Enable the function. 1: Disable the function. IOCB [7] Undefined. The default value is Zero. IOCC (Port 9 LED Sink Capacity Control Register) Default Value: (0B_0000_0000) 7 0 6 P96 5 P95 4 0 3 P93 2 P92 1 P91 0 P90 IOCC [0~3,5,6] LED sink control bit. These bits are used to enable the LED sink capacity of P90 ~ P93, P95, and P96. 0: Disable the LED sink capacity of respective pin. 1: Enable the LED sink capacity of respective pin. IOCC [4,7] Undefined. The default value is Zero. This spec. may change without further notice. 20 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary IOCD (Port 9 Pull High Control Register) Default Value: (0B_1111_1111) 7 1 6 /PH96 5 /PH95 4 1 3 /PH93 2 /PH92 1 /PH91 0 /PH90 IOCD [0~6] These bits control the 200KOhm pull-high resistor of individual pins in Port 9. 1: Disable the function of pull-high. 0: Enable the function of pull-high. IOCE (Special Function Control Register) Default Value: (0B_1101_01111) 7 /Dual clock 6 /WUE 5 WTE 4 RUN 3 Device_Resume 2 /PU8 1 /PU6 0 /PU5 IOCE [0,1,2] Port 5, Port 6, and Port 8 pull-high control bits. 1: Disable 0: Enable IOCE [3] Device Resume control bit. Writing this bit to "1" can generate Device Resume signal on USB bus. As long as the USB bus is not idle, this bit will be cleared at the same time. Run bit. This bit can be cleared by the firmware and set during power-on, or by the hardware at the falling edge of wake-up signal. When this bit is cleared, the clock system is disabled and the MCU enters into Power down mode. At the transition of wake-up signal from high to low, this bit is set to enable the clock system. 1: Run mode. The EM78M611 is working normally. 0: Sleep mode. The EM78M611 is in power down mode. IOCE [5] WatchDog Timer enable bit. The bit disable/enables the WatchDog Timer. 1: Enable WDT. 0: Disable WDT. IOCE [6] Enable the wake-up function as triggered by port-changed. This bit is set by UDC. 1: Disable the wake-up function. 0: Enable the wake-up function. IOCE [4] This spec. may change without further notice. 21 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary IOCE [7] Dual clock Control bit. This bit is used to select the frequency of system clock. When this bit is cleared, the MCU will run on very low frequency for power saving and the UDC will stop working. 1: Selects EM78M611 to run on normal frequency. 0: Selects to run on slow frequency. IOCF (Interrupt Mask Register) 7 USB Host Resume_IE 6 SE2_IE 5 SE1_IE Default ValueG 4 Port7 state change_1E 3 (0B_0000_0000) 2 USB Suspend_IE 1 EP0_IE 0 TCC_IE USB Reset_IE IOCF [0~7] TCC / EP0 / USB Suspend / USB Reset / Port 7 State Change / SE1 / SE2 / USB Host Resume interrupt enable bits. These eight bits control the function of TCC interrupt, EP0 interrupt, USB Suspend interrupt, USB Reset interrupt, Port7 State Change interrupt, SE1 pattern detection interrupt, SE2 pattern detection interrupt and USB Host Resume interrupt respectively. Individual interrupt is enabled by setting its associated control bit in the IOCF to "1." 1: Enable Interrupt. 0: Disable Interrupt. Only when the global interrupt is enabled by the ENI instruction that the individual interrupt will work. After DISI instruction, any interrupt will not work even if the respective control bits of IOCF are set to 1. The USB Host Resume Interrupt works only under Dual clock mode. This is because when the MCU is under sleep mode, it will be waked up by the UDC Resume signal automatically. 8.2.1.3 Extra Control Register Five extra control registers are available to control special functions. The five registers are ERA (AD Control register), ERB (AD_LSB), ERC (AD_MSB), ERD (AD_Rate), and ERE (PWM Control register). Remember to set IOCA[3] before accessing these five registers. The operating method is same as other control registers. More detailed descriptions of the registers are provided in Section 8.7 to 8.9. This spec. may change without further notice. 22 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.2.2 USB Application FIFOs For USB Application, EM78M611 provides an 8-byte First-In-First-Out (FIFO) buffer for each endpoint. The buffer cannot be accessed directly. However, a corresponding Data Byte Pointer register for each endpoint is made available to address the individual byte of the FIFO buffer. The content of the individual byte will map to a special register. 8.2.3 E2PROM Four bytes of E2PROM are located in the R2C ~ R2F of Bank 3. The stored data of E2PROM are not erased when the power is off and can be read and rewritten by firmware. In some special case of application, for example, cordless keyboard controller, it can store important data, such as the cordless keyboard's device identical number. There is a control register, RA (address : 0x0A in Bank1) that controls the E2PROM, that is, to read, write, or to erase the data from E2PROM. Writing a command into this register will execute an action to E2PROM. The command value is defined in the following table. Note that there is an execution time lapse for each command. Before writing the next command into the control register, allow enough time for the E2PROM to finish the previous command. Command Value 0B_0000_0000 0B_0000_0001 0B_0000_0010 0B_0000_0011 Action Read Write Erase Disable Execution Time 1ms 9ms 128ms N.A. 8.3 USB Application EM78M611 is designed specially for USB device application and has many powerful functions that help the firmware to free itself from complex situation in various aspects of USB application. 8.3.1 Auto-Detect PS/2 or USB Mode When the EM78M611 is connected to the bus, it will auto-detect and identify which type of bus (USB or PS/2) it is connected to. The condition that influences auto-detect function is described below: 1. After a Power-on reset, the initial value of IOCA [0,1] is 0b00. Thus the operation mode is "Detect mode" and the D+ and D- IO pins are internal pulled high by 200KOhm to VDD. 2. The firmware checks the state of R7 [4,5]. If the state of this two bit is 0b00, set the IOCA [0] to "1" to define the "USB mode." Otherwise, set the IOCA [1] to "1," to define "PS/2 mode." This spec. may change without further notice. 23 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 3. When the operation mode is defined as "USB mode," the D- IO pin will be internal pulled high by a 1.5KOhm resistor to 3.3V, which is output from a built-in regulator. 4. If the operation mode is in "PS/2 mode," both of the PS/2 interface IO pins are internal pulled high by a 2.2KOhm resistor to VDD. {NOTE] If the auto-detect function is not used, the firmware should set the operation mode, either USB mode or PS/2 mode, in the beginning of program. An additional mode, "USB Test Mode" is also available. This mode has no load on D+ and D- IO pins, and can only be used in USB Application case. Therefore, an external 1.5KOhm resistor is needed to pull up D- IO pin to 3.3V. Under PS/2 mode, both PS/2 pins are programmed to generate an interrupt. After setting the P.74 ~ P.77 State changed Interrupt Enable bit, the MCU will interrupt while the state of these four pins changes. 8.3.2 USB Device Controller The USB Device Controller (UDC) built-in in the EM78M611 can interpret the USB Standard Command and response automatically without involving firmware. The embedded Series Interface Engine (SIE) handles the serialization and deserialization of actual USB transmission. Thus, a developer can concentrate his efforts more in perfecting the device actual functions and spend less energy in dealing with USB transaction. The UDC handles and decodes most Standard USB commands defined in the USB Specification Rev1.1. If UDC receives an unsupported command, it will set a flag to notify MCU the receipt of such command. The Standard Commands that EM78M611 supports includes; Clear Feature, Get Configuration, Get Interface, Get Status, Set Address, Set Configuration, Set Feature, and Set Interface. Each time UDC receives a USB command, it writes the command into EP0's FIFO. Only when it receives unsupported command that the UDC will notify the MCU through interrupt. Therefore, EM78M611 is very flexible under USB application because the developer can freely choose the method of decoding the USB command as dictated by different situation. 8.3.3 Device Address and Endpoints EM78M611 supports one device address and three endpoints, EP0 for control endpoint, EP1 and EP2 for interrupt endpoint. Sending data to USB host in EM78M611 is very easy. Just write data into EP's FIFO, then set flag, and the UDC will handle the rest. It will then confirm that the USB host has received the correct data from EM78M611. This spec. may change without further notice. 24 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.4 Reset The EM78M611 provides three types of reset: (1) Power-on Reset, (2) WatchDog Reset, and (3) USB Reset. 8.4.1 Power-On Reset Power-on Reset occurs when the device is attached to power and a reset signal is initiated. The signal will last until the MCU becomes stable. After a Power-on Reset, the MCU enters into following predetermined states (see below), and then, it is ready to execute the program. a. The program counter is cleared. b. The TCC timer and WatchDog timer are cleared. c. Special registers and Special Control registers are all set to initial value. The MCU also has a low voltage detector that detects low output power condition. Whenever the output voltage of the 3.3V regulator decreases to below 2.2V, a reset signal is set off. 8.4.2 WatchDog Reset When the WatchDog timer overflows, it causes the WatchDog to reset. After it resets, the program is executed from the beginning and some registers will be reset. The UDC however, remains unaffected. 8.4.3 USB Reset When UDC detects a USB Reset signal on USB Bus, it interrupts the MCU, then proceed to perform the specified process that follows. After a USB device is attached to the USB port, it cannot respond to any bus transactions until it receives a USB Reset signal from the bus. This spec. may change without further notice. 25 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.5 Saving Power Mode The EM78M611 provides two options of power-saving modes for energy conservation, i.e., Power Down mode and Dual clock mode. 8.5.1 Power Down Mode The EM78M611 enters into Power Down mode by clearing the RUN register (IOCE[4]). During this mode, the oscillator is turned off and the MCU goes to sleep. It will wake up when signal from USB host is resumed, or when the WatchDog reset or the input port state changes. If the MCU wakes up when I/O port status changes, the direction of I/O port should be set at input direction, then read the state of port. For example: : // Set the Port 6 to input port MOV A , 0XFF IOW PORT6 // Read the state of Port 6 MOV PORT6, PORT6 // Clear the RUN bit IOR 0XE AND A , 0B11101111 IOW 0XE : : If the MCU is awaken by a USB Resume signal, the next instruction will be executed and one flag, RC[3] will be set to 1. 8.5.2 Dual Clock Mode The EM78M611 has one internal oscillator for power saving application. Clearing the Bit IOCE [7] will enable the low frequency oscillator. At the same time, the external oscillator will be turned off. Then the MCU will run under very low frequency to conserve power. Four types of frequency are available for selection in setting Bits IOCA [6, 7]. The USB Host Resume Interrupt can only be used in this mode. If this interrupt is enabled, the MCU will be interrupted when the USB Suspend signal is detected on USB Bus. This spec. may change without further notice. 26 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.6 Interrupt The EM78611 has one interrupt vectors in 0x0001. When an interrupt occurs during the MCU running program, it will jump to the interrupt vector (0x0001) and execute the instructions sequentially from interrupt vector. RF is the interrupt status register, which records the interrupt status in the relative flags/bits. The interrupt condition could be one of the following: 1. TCC Overflow: When the Timer Clock / Counter Register (R1) overflows, the status flag RF[0] will be set to 1. Its interrupt vector is 0X0001. When the input signals in Port 7 changes, the status flag RF[4] will be set to 1. Its interrupt vector is 0X0001. 2. Port7 State Change: 3. SE1 Pattern Detection Interrupt Conditions: If the Pattern Detection Application function is enabled, there will be four conditions with which interruption is generated, and the status flag RF[5] is set to 1 (interrupt vector is 0X0001). a) Signal from P.92 changes to low, and Pattern Counter value is bigger than R11 register value. b) Signal from P.92 changes to high, and Pattern Counter value bigger than R10 register value. c) P.92 stays high, and Pattern Counter value equal 0XFF. d) P.92 stays low, and Pattern Counter value equal 0XFF. 4. SE2 Pattern Counter Interrupt Conditions: If the Pattern Detection Application function is enabled, there will be three conditions with which interruption is generated and the status flag RF[6] is set to 1(interrupt vector is 0X0001). a) Signal from P.93 changes to low, and Pattern Counter value is bigger than R13 register value. b) Signal from P.93 changes to high, and Pattern Counter value is bigger than R12 register value. c) P.93 stays high, and Pattern Counter value equal 0XFF. d) P.93 stays low, and Pattern Counter value equal 0XFF. This spec. may change without further notice. 27 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 5. EP0 interrupt: When the UDC successfully accepts a setup transaction from host to EndPoint0, the status flag RF[1] is set to 1. Its interrupt vector is 0X0001 When UDC detects a USB Suspend signal on USB bus, the status flag RF[2] is set to 1. Its interrupt vector is 0X0001. When the UDC detects a USB Reset signal on USB bus, the status flag R[3] is set to 1. Its interrupt vector is 0X0001. When UDC detects that the USB bus is no longer in Suspend condition and without Device Resume signal, the status flag R[7] is set to 1. Its interrupt vector is 0X0001. 6. USB suspend: 7. USB Reset: 8. USB Host Resume: IOCF is an interrupt mask register which can be set bit by bit. While their respective bit is written to 0, the hardware interrupt will inhibit, that is, the EM78M611 will not jump to the interrupt vector to execute instructions. But the interrupt status flags still records the conditions no matter whether the interrupt is masked or not. The interrupt status flags must be cleared by firmware before leaving the interrupt service routine and enabling interrupt. The global interrupt is enabled by the ENI (RETI) instruction and is disabled by the DISI instruction. 8.7 Pattern Detect Application (PDA) 8.7.1 Function Description This function is designed for the serial signal transmission, e.g., the transmission between a wireless device and its receiver box. The EM78M611 has two sets of built-in Pattern Detect Application block that ensures the EM78M611 is equipped with a compound device, such as the receiver box controller for a wireless keyboard paired with a wireless mouse. Pattern Detect Application (PDA) can calculate the length of one pattern and interrupt the MCU while the serial signal is transiting from high to low (or vise-versa). Then the MCU reads the length value from a specified register. 8.7.2 Control Register The PDA includes an enable control bit, one control register and four length counter registers in 0x10 ~0x13. IOCA [2] PDA Enable Control Bit. When this bit is set, the PDA function starts and the P92 and P93 become input pin automatically to sample the serial signal. 1 : enable PDA function. 0 : disable PDA function. This spec. may change without further notice. 28 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary RB (PDA Control Register) Default Value: (0B_0000_0000) 7 6 5 SR.2 4 SR.1 3 SR.0 2 DB2 1 DB1 0 DB0 SE2.F SE1.F This register is used to define two parameters of PDA function; signal sampling rate and debounce length. When a pattern ends, the value in the counter is loaded into its respective register and the RB[6] or RB[7] is set to indicate which type of pattern (high or low) is at its end or which type of pattern counter is on overflow. 0: low pattern. 1: high pattern. R10 (P.92 Low Pattern Counter) This register records the length of P.92 in low status. R11 (P.92 High Pattern Counter) This register records the length of P.92 in high status. R12 (P.93 Low Pattern Counter) This register record the length of P.93 in low status. R13 (P.93 High Pattern Counter) This register records the length of P.93 in high status. R10~R13 function as general registers if this function is not enabled. Once the enabled bit is set, these four registers will be loaded with the value of pattern counter. 8.7.3 Sampling Rate and Debounce Length Although the two pattern detect pins are separate, and each pin has its own pattern counter. Both pins use the same Sampling Rate and Debounce Length parameters. The PDA samples the serial signal every fixed interval. The pattern counter will increase by one at sampling time if the signal remains unchanged. If the signal is at high state, then the "high pattern counter" will increase; otherwise the "low pattern counter" increases. As long as the signal state changes, the PDA will debounce signal and load the value of pattern counter into the respectively register for the firmware to read. For example, if the signal in P.92 is in "low" state, the low counter of P.92 will counts continuously until the state of the input signal in P.92 changes. When the state of change occurs (in this case, the signal changes from "low" to "high" state), the PDA will take for a time break (which is equal the result of sampling interval multiplied by the debounce length), to avoid possible noise. After the debounce length time, if the signal remains in high state, the high pattern counter will start to count and This spec. may change without further notice. 29 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary load the low pattern counter's value into R10. At the same time, RB[6] is cleared to indicate the low pattern is over. The correlation between the value of control register and debounce time are as follows: DB.2 DB.1 DB.0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Debounce Time No Sampling clock. 1 Sampling clock 2 Sampling clock 3 Sampling clock. 4 Sampling clock 5 Sampling clock 6 Sampling clock 7 Sampling clock Now consider another situation of this case, where the signal of P92 always stays "low". The low pattern counter of P92 will eventually overflow. Once the counter overflows, the content of the counter will also be loaded into R10, that is, the register is written to 0xFF, then the counter is reset to count from zero again. If the hardware interrupt of PDA function is enabled, (IOCF[5] is equal to "1"), then the program will go to 0x0001 to execute interrupt routine while the content of a pattern counter is loaded into the register. The correlation between the value of control register and actual sampling rate are as shown below: SR.2 SR.1 SR.0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sampling Rate (External oscillator frequency = 6MHz) N.A. N.A. 1500 (Count / mSec) 750 (Count / mSec) 375 (Count / mSec) 188 (Count / mSec) 94 (Count / mSec) 47 (Count / mSec) Sampling Rate (External oscillator frequency = 12MHz) N.A. N.A. N.A. 1500 (Count/ mSec) 750 (Count / mSec) 375 (Count / mSec) 188 (Count / mSec) 94 (Count / mSec) After the PDA function is enabled (by setting IOCA[2] to 1), user can write a default value to the High Pattern counter register and Low Pattern counter register. Then set the corresponding interrupt enable bit (IOCF[5]). When the counting value of one "H" pattern is bigger than the default value of R11, the Pattern Detecting interrupt will be generated. Similarly, if the counting value of one "L" pattern is bigger than the default value of R10, the Low Pattern Detecting interrupt will occur. Thus, the EM78M611 is notified and aware that one effective pattern is received from P.92. If user has no need of these two interrupts, they can be masked. The new value of counting This spec. may change without further notice. 30 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary a pattern still will be loaded to the R10 and R11. The firmware must poll and determine whether the value of these two registers had changed or not. 8.7.4 Example Initial Setting : IOCA[5:3] = 5 : Setting Prescaler. Setting 1:32. IOR IOCA AND A,@0XC7 OR A,@0X28 IOW IOCA RB[3:0] = 3 : Setting Debonce Times. MOV A,@0X03 MOV RB,A R10~R13 = 150(800uS) : Setting compare value. MOV A,@150 MOV R10~13,A IOCA[2] : Enabling RF function : IOR IOCA OR A,@0X04 IOW IOCA ;0000_0 1 00 ;11 00_0 111 ;00 10_1 000 The active of the RF timing counter : After setting. Assume that the T1 is the High pattern counter and the T2 is the Low pattern counter. The PDA function will compare R11 or R13 with T1 or compare R10 or R12 with T2. If T1 >= R11 , then setting RB[4] = 1 and making RF1 interrupting. If T1 >= R13 , then setting RB[5] = 1 and making RF2 interrupting. If T2 >= R10 , then setting RB[4] = 0 and making RF1 interrupting. If T2 >= R12 , then setting RB[5] = 0 and making RF2 interrupting. After interrupting. The program will check Timing Count & save state. R10 : The low signal counter of the 1st RF module that inputted from P92. R11 : The high signal counter of the 1st RF module that inputted from P92. R12 : The low signal counter of the 2nd RF module that inputted from P93. R13 : The high signal counter of the 2nd RF module that inputted from P93. This spec. may change without further notice. 31 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.8 Pulse Width Modulation (PWM) 8.8.1 Function Description In PWM mode, both of PWM1 (P.92) and PWM2 (P.93) produce plus programmable signal of up to 8-bits resolution. The PWM Period is defined as 0xFF * Timer Counter Clock. The Timer Counter clock source is controlled by an extra control register, ERE. For example; if the Clock source is 1MHz, then the Period will be 255u seconds. Period = 255 * (1/Timer Counter Clock) Period (0xFF * Clock) Duty Cycle Fig.8.9.2 The PWM Output Timing 8.8.2 Duty Cycle The PWM duty cycle is defined by writing to the R10/R11 Register for PWM1/PWM2. Duty Cycle = ( R10 / 255 ) * 100% for PWM1 ( R11 / 255 ) * 100% for PWM2 8.8.3 Control Register R10 ( PWM1 Duty Cycle Register) A specified value keeps the output of PWM1 to remain at high in a Period. R11 ( PWM2 Duty Cycle Register) A specified value keeps the output of PWM2 to remain at high in a Period. This spec. may change without further notice. 32 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary ERE(PWM Control Register) Default Value: (0B_0000_0001) 7 PEN2 6 PEN1 5 4 3 2 PS2 1 PS1 0 PS0 ERE [0~2] PWM Clock Prescaler. PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Clock(Hz) Fosc/3 Fosc/6 Fosc/12 Fosc/24 Fosc/48 Fosc/96 Fosc/192 Fosc/384 Period/255 (s) 0.5u 1u 2u 4u 8u 16u 32u 64u ERE [6,7] PWM1/PWM2 Enable Bit 0:Disable 1:Enable 8.9 Analog-To-Digital Converter (ADC) 8.9.1 Function Description The Analog to Digital converter consists of a 5-bit analog multiplexer, one Control Register (ERA), and two data registers (RBS & RCS) for 10-bit resolution. The ADC module utilizes successive approximation to convert the unknown analog signal to a digital value. The result is fed to the ADDATA. Input channels are selected by the analog input multiplexer via the ADCS/RAS bits AD0~AD4. 10-bit resolution: 0x00-00~0xC0-FF (0b11000000-11111111) Start (0x00-00): Full (0xC0-FF): 0 Vref~(1/1024)*Vref (1023/1024)*Vref~Vref Converting Time: 12 clock time of internal clock source This spec. may change without further notice. 33 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 8.9.2 Control Register ERA (AD Channel Select Register) Default Value: (0B_0001_1111) 7 ADC 6 0 5 0 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0 ERA [0~4]:AD Channel Selector AD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 AD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 I/O Port P50 P51 P52 P53 P54 P55 P56 P57 P80 P81 P82 P83 P84 P85 P86 P87 P60 P61 P62 P63 P64 P65 P66 P67 ERA [7] AD Converter ready flag. 0 1 1: Start AD Converting (set by firmware). 0: When AD finishes converting and has moved digital data into AD Data Register, this bit will be set by hardware. [NOTE] Hardware can enable this function only at AD Channel Selector of the functional I/O port. After Power-on reset, the initial value of this register is 0b0001 1111. This spec. may change without further notice. 34 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary ERB (AD LSB Data Register) Default Value: (0B_0000_0000) 7 Bit 1 6 Bit 0 5 0 4 0 3 0 2 0 1 0 0 0 AD Digital Data LSB 8 bits. ERC (AD MSB Data Register) Default Value: (0B_0000_0000) 7 Bit 9 6 Bit 8 5 Bit 7 4 Bit 6 3 Bit 5 2 Bit 4 1 Bit 3 0 Bit 2 AD Digital Data MSB 2 bits. ERD (AD Control Register) Default Value: (0B_0000_0000) 7 0 6 0 5 0 4 0 3 0 2 1 ADPS1 0 ADPS0 ERD [0 1]:The clock source of AD converting time. 00: 256kHz 01: 128kHz 10: 64kHz 11: 32kHz 9. Absolute Maximum Ratings Symbol Temperature under bias Storage temperature Input voltage Output voltage Min 0 -65 -0.5 -0.5 Max 70 150 6.0 6.0 Unit C C V V This spec. may change without further notice. 35 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary 10. DC Electrical Characteristic (T = 25C, VDD=5V, VSS=0V) Symble Parameter Condition 3.3V Regulator VRag VResetL VResetH Output voltage of 3.3v Regulator Low Power Reset detecting low Voltage Low Power Reset detecting high Voltage MCU operating IIL VIHX VILX ICC1 Input Leakage Current for input pins Clock Input High Voltage Clock Input Low Voltage VDD operating supply current - Normal frequency operation mode VDD operating supply current - Normal frequency operation mode VDD operating supply current - Dual clock mode Operating supply current 1 - Power down mode Operating supply current 2 - Power down mode VIN=VDD,VSS OSCI OSCI Crystal type Freq. = 6MHz Output pins floating Crystal type Freq. = 12MHz Output pins floating RC oscillation type Freq. = 256kHz Ouput pins floating All input and I/O pins at VDD Output pins floating WDT disabled All input and I/O pins at VDD Output pins floating WDT enable GPIO Pins VIH VIL VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 Input High Voltage Input Low Voltage Output High Voltage (P70~P73,P76 and P77) Output High Voltage (P74, P75) Output High Voltage (Port5 & Port6 & Port8 and P90~P93, P95, P96) Output Low Voltage (P76 and P77 normal mode) Output Low Voltage (P74, P75) Output Low Voltage (P70~P73,P76 and P77 sink LED) Port 5 & Port 6 & Port 7 & Port 8 & Port 9 Port 5 & Port 6 & Port 7 & Port8 & Port 9 ISink = 10.0mA VDD = 5V ISink = 5.0mA VDD = 5V ISink = 10.0mA VREG = 3.3V ISink = 10.0mA VDD = 5V ISink = 5.0mA VDD = 5V ISink = 10.0mA VDD = 5V 2.0 2.4 2.4 2.4 0.4 0.4 3 0.8 V V V V V V V V 2.5 O1 1.0 10 gA V V mA 3.0 VDD = 4.4V ~ 5.25V 3.0 3.3 3.6 2.2 V V V Min Type Max Unit ICC2 - - 20 mA ICC3 - - 250 gA ISB1 - - 80 gA ISB2 - - 100 gA This spec. may change without further notice. 36 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary VOL4 VOL5 IPH1 Output Low Voltage (P90 ~ P96 normal mode) Output Low Voltage (P90 ~ P96 sink LED) Input current with pull-high resister ( Port 5, 6, 8, P.90 ~ P.93, P.95 ~ P.96) Input current with pull-high resister ( P.74 ~ P.77) ISink = 10.0mA VREG = 3.3V ISink = 10.0mA VREG = 3.3V Input pin with pull-high resistor (25kOhm) VIN = VSS Input pin with pull-high resistor (2.2kOhm) VIN = VSS USB Interface VOH VOL VDI VCM VSE CIN VRG Static Output High Static Output Low Differential Input Sensitivity Differential Input Command Mode Range Single Ended Receiver Threshold Transceiver Capacitance Output Voltage of Internal Regulator USB operation Mode USB operation Mode 2.8 0.2 0.8 0.8 3.0 3.6 0.3 2.5 2.0 20 3.6 V V V V V pF V 0.4 1 V V gA 125 IPH2 2.27 mA This spec. may change without further notice. 37 06/ 18/ 2003(V1.0) EM78M611 Universal Serial Bus Microcontroller Series Preliminary (c) 2003 ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan, ROC, 05/2003 The contents of this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility for errors that may appear in this specification. ELAN Microelectronics makes no commitment to update, or to keep current, the information contained in this specification. The products described herein are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics products in such applications are not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: +886 3 5639977 Fax: +886 3 5639966 http://www.emc.com.tw Hong Kong Office: Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2838-8715 Fax: +852 2838-0497 This spec. may change without further notice. 38 06/ 18/ 2003(V1.0) |
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